ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC) -------------------- Required properties: -------------------- - compatible : Should be "st,stm32mp1-ddr" for STM32MP15x Should be "st,stm32mp13-ddr" for STM32MP13x - reg : controleur (DDRCTRL) and phy (DDRPHYC) base address - clocks : controller clocks handle - clock-names : associated controller clock names the "ddrphyc" clock is used to check the DDR frequency at phy level according the expected value in "mem-speed" field the next attributes are DDR parameters, they are generated by DDR tools included in STM32 Cube tool They are required only in SPL, when TFABOOT is not activated. info attributes: ---------------- - st,mem-name : name for DDR configuration, simple string for information - st,mem-speed : DDR expected speed for the setting in kHz - st,mem-size : DDR mem size in byte controlleur attributes: ----------------------- - st,ctl-reg : controleur values depending of the DDR type (DDR3/LPDDR2/LPDDR3) for STM32MP15x and STM32MP13x: 25 values are requested in this order MSTR MRCTRL0 MRCTRL1 DERATEEN DERATEINT PWRCTL PWRTMG HWLPCTL RFSHCTL0 RFSHCTL3 CRCPARCTL0 ZQCTL0 DFITMG0 DFITMG1 DFILPCFG0 DFIUPD0 DFIUPD1 DFIUPD2 DFIPHYMSTR ODTMAP DBG0 DBG1 DBGCMD POISONCFG PCCFG - st,ctl-timing : controleur values depending of frequency and timing parameter of DDR for STM32MP15x and STM32MP13x: 12 values are requested in this order RFSHTMG DRAMTMG0 DRAMTMG1 DRAMTMG2 DRAMTMG3 DRAMTMG4 DRAMTMG5 DRAMTMG6 DRAMTMG7 DRAMTMG8 DRAMTMG14 ODTCFG - st,ctl-map : controleur values depending of address mapping for STM32MP15x and STM32MP13x: 9 values are requested in this order ADDRMAP1 ADDRMAP2 ADDRMAP3 ADDRMAP4 ADDRMAP5 ADDRMAP6 ADDRMAP9 ADDRMAP10 ADDRMAP11 - st,ctl-perf : controleur values depending of performance and scheduling for STM32MP15x: 17 values are requested in this order SCHED SCHED1 PERFHPR1 PERFLPR1 PERFWR1 PCFGR_0 PCFGW_0 PCFGQOS0_0 PCFGQOS1_0 PCFGWQOS0_0 PCFGWQOS1_0 PCFGR_1 PCFGW_1 PCFGQOS0_1 PCFGQOS1_1 PCFGWQOS0_1 PCFGWQOS1_1 for STM32MP13x: 11 values are requested in this order SCHED SCHED1 PERFHPR1 PERFLPR1 PERFWR1 PCFGR_0 PCFGW_0 PCFGQOS0_0 PCFGQOS1_0 PCFGWQOS0_0 PCFGWQOS1_0 phyc attributes: ---------------- - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3) for STM32MP15x: 11 values are requested in this order PGCR ACIOCR DXCCR DSGCR DCR ODTCR ZQ0CR1 DX0GCR DX1GCR DX2GCR DX3GCR for STM32MP13x: 9 values are requested in this order PGCR ACIOCR DXCCR DSGCR DCR ODTCR ZQ0CR1 DX0GCR DX1GCR - st,phy-timing : phy values depending of frequency and timing parameter of DDR for STM32MP15x and STM32MP13x: 10 values are requested in this order PTR0 PTR1 PTR2 DTPR0 DTPR1 DTPR2 MR0 MR1 MR2 MR3 for STM32MP13x: 6 values are requested in this order DX0DLLCR DX0DQTR DX0DQSTR DX1DLLCR DX1DQTR DX1DQSTR Example: / { soc { ddr: ddr@0x5A003000{ compatible = "st,stm32mp1-ddr"; reg = <0x5A003000 0x550 0x5A004000 0x234>; clocks = <&rcc_clk AXIDCG>, <&rcc_clk DDRC1>, <&rcc_clk DDRC2>, <&rcc_clk DDRPHYC>, <&rcc_clk DDRCAPB>, <&rcc_clk DDRPHYCAPB>; clock-names = "axidcg", "ddrc1", "ddrc2", "ddrphyc", "ddrcapb", "ddrphycapb"; st,mem-name = "DDR3 2x4Gb 533MHz"; st,mem-speed = <533000>; st,mem-size = <0x40000000>; st,ctl-reg = < 0x00040401 /*MSTR*/ 0x00000010 /*MRCTRL0*/ 0x00000000 /*MRCTRL1*/ 0x00000000 /*DERATEEN*/ 0x00800000 /*DERATEINT*/ 0x00000000 /*PWRCTL*/ 0x00400010 /*PWRTMG*/ 0x00000000 /*HWLPCTL*/ 0x00210000 /*RFSHCTL0*/ 0x00000000 /*RFSHCTL3*/ 0x00000000 /*CRCPARCTL0*/ 0xC2000040 /*ZQCTL0*/ 0x02050105 /*DFITMG0*/ 0x00000202 /*DFITMG1*/ 0x07000000 /*DFILPCFG0*/ 0xC0400003 /*DFIUPD0*/ 0x00000000 /*DFIUPD1*/ 0x00000000 /*DFIUPD2*/ 0x00000000 /*DFIPHYMSTR*/ 0x00000001 /*ODTMAP*/ 0x00000000 /*DBG0*/ 0x00000000 /*DBG1*/ 0x00000000 /*DBGCMD*/ 0x00000000 /*POISONCFG*/ 0x00000010 /*PCCFG*/ >; st,ctl-timing = < 0x0080008A /*RFSHTMG*/ 0x121B2414 /*DRAMTMG0*/ 0x000D041B /*DRAMTMG1*/ 0x0607080E /*DRAMTMG2*/ 0x0050400C /*DRAMTMG3*/ 0x07040407 /*DRAMTMG4*/ 0x06060303 /*DRAMTMG5*/ 0x02020002 /*DRAMTMG6*/ 0x00000202 /*DRAMTMG7*/ 0x00001005 /*DRAMTMG8*/ 0x000D041B /*DRAMTMG1*/4 0x06000600 /*ODTCFG*/ >; st,ctl-map = < 0x00080808 /*ADDRMAP1*/ 0x00000000 /*ADDRMAP2*/ 0x00000000 /*ADDRMAP3*/ 0x00001F1F /*ADDRMAP4*/ 0x07070707 /*ADDRMAP5*/ 0x0F070707 /*ADDRMAP6*/ 0x00000000 /*ADDRMAP9*/ 0x00000000 /*ADDRMAP10*/ 0x00000000 /*ADDRMAP11*/ >; st,ctl-perf = < 0x00001201 /*SCHED*/ 0x00001201 /*SCHED*/1 0x01000001 /*PERFHPR1*/ 0x08000200 /*PERFLPR1*/ 0x08000400 /*PERFWR1*/ 0x00010000 /*PCFGR_0*/ 0x00000000 /*PCFGW_0*/ 0x02100B03 /*PCFGQOS0_0*/ 0x00800100 /*PCFGQOS1_0*/ 0x01100B03 /*PCFGWQOS0_0*/ 0x01000200 /*PCFGWQOS1_0*/ 0x00010000 /*PCFGR_1*/ 0x00000000 /*PCFGW_1*/ 0x02100B03 /*PCFGQOS0_1*/ 0x00800000 /*PCFGQOS1_1*/ 0x01100B03 /*PCFGWQOS0_1*/ 0x01000200 /*PCFGWQOS1_1*/ >; st,phy-reg = < 0x01442E02 /*PGCR*/ 0x10400812 /*ACIOCR*/ 0x00000C40 /*DXCCR*/ 0xF200001F /*DSGCR*/ 0x0000000B /*DCR*/ 0x00010000 /*ODTCR*/ 0x0000007B /*ZQ0CR1*/ 0x0000CE81 /*DX0GCR*/ 0x0000CE81 /*DX1GCR*/ 0x0000CE81 /*DX2GCR*/ 0x0000CE81 /*DX3GCR*/ >; st,phy-timing = < 0x0022A41B /*PTR0*/ 0x047C0740 /*PTR1*/ 0x042D9C80 /*PTR2*/ 0x369477D0 /*DTPR0*/ 0x098A00D8 /*DTPR1*/ 0x10023600 /*DTPR2*/ 0x00000830 /*MR0*/ 0x00000000 /*MR1*/ 0x00000208 /*MR2*/ 0x00000000 /*MR3*/ >; status = "okay"; }; }; };