J721S2 and AM68 Platforms

Introduction:

The J721S2 family of SoCs are part of K3 Multicore SoC architecture platform targeting automotive applications. They are designed as a low power, high performance and highly integrated device architecture, adding significant enhancement on processing power, graphics capability, video and imaging processing, virtualization and coherent memory support.

The AM68 Starter Kit/Evaluation Module (EVM) is based on the J721S2 family of SoCs. They are designed for machine vision, traffic monitoring, retail automation, and factory automation.

The device is partitioned into three functional domains, each containing specific processing cores and peripherals:

  1. Wake-up (WKUP) domain:
    • ARM Cortex-M4F processor, runs TI Foundational Security (TIFS)

  2. Microcontroller (MCU) domain:
    • Dual core ARM Cortex-R5F processor, runs device management and SoC early boot

  3. MAIN domain:
    • Dual core 64-bit ARM Cortex-A72, runs HLOS

More info can be found in TRM: https://www.ti.com/lit/pdf/spruj28

Platform information:

Boot Flow:

Below is the pictorial representation of boot flow:

../../_images/boot_diagram_k3_current.svg
  • On this platform, “TI Foundational Security” (TIFS) functions as the security enclave master while “Device Manager” (DM), also known as the “TISCI server” in TI terminology, offers all the essential services.

  • As illustrated in the diagram above, R5 SPL manages power and clock services independently before handing over control to “DM”. The A72 or the C7x (Aux core) software components request TIFS/DM to handle security or device management services.

Sources:

Note

The TI Firmware required for functionality of the system can be one of the following combination (see platform specific boot diagram for further information as to which component runs on which processor):

  • TIFS - TI Foundational Security Firmware - Consists of purely firmware meant to run on the security enclave.

  • DM - Device Management firmware also called TI System Control Interface server (TISCI Server) - This component purely plays the role of managing device resources such as power, clock, interrupts, dma etc. This firmware runs on a dedicated or multi-use microcontroller outside the security enclave.

OR

  • SYSFW - System firmware - consists of both TIFS and DM both running on the security enclave.

Build procedure:

  1. Setup the environment variables:

Generic environment variables

S/w Component

Env Variable

Description

All Software

CC32

Cross compiler for ARMv7 (ARM 32bit), typically arm-linux-gnueabihf-

All Software

CC64

Cross compiler for ARMv8 (ARM 64bit), typically aarch64-linux-gnu-

All Software

LNX_FW_PATH

Path to TI Linux firmware repository

All Software

TFA_PATH

Path to source of Trusted Firmware-A

All Software

OPTEE_PATH

Path to source of OP-TEE

Board specific environment variables

S/w Component

Env Variable

Description

U-Boot

UBOOT_CFG_CORTEXR

Defconfig for Cortex-R (Boot processor).

U-Boot

UBOOT_CFG_CORTEXA

Defconfig for Cortex-A (MPU processor).

Trusted Firmware-A

TFA_BOARD

Platform name used for building TF-A for Cortex-A Processor.

Trusted Firmware-A

TFA_EXTRA_ARGS

Any extra arguments used for building TF-A.

OP-TEE

OPTEE_PLATFORM

Platform name used for building OP-TEE for Cortex-A Processor.

OP-TEE

OPTEE_EXTRA_ARGS

Any extra arguments used for building OP-TEE.

Set the variables corresponding to this platform:

export CC32=arm-linux-gnueabihf-
export CC64=aarch64-linux-gnu-
export LNX_FW_PATH=path/to/ti-linux-firmware
export TFA_PATH=path/to/trusted-firmware-a
export OPTEE_PATH=path/to/optee_os
export UBOOT_CFG_CORTEXR=j721s2_evm_r5_defconfig
export UBOOT_CFG_CORTEXA=j721s2_evm_a72_defconfig
export TFA_BOARD=generic
export TFA_EXTRA_ARGS="K3_USART=0x8"
# The following is not a typo, j784s4 is the OP-TEE platform for j721s2
export OPTEE_PLATFORM=k3-j784s4
export OPTEE_EXTRA_ARGS="CFG_CONSOLE_UART=0x8"
  1. Trusted Firmware-A:

# inside trusted-firmware-a source
make CROSS_COMPILE=$CC64 ARCH=aarch64 PLAT=k3 SPD=opteed $TFA_EXTRA_ARGS \
     TARGET_BOARD=$TFA_BOARD
  1. OP-TEE:

# inside optee_os source
make CROSS_COMPILE=$CC32 CROSS_COMPILE64=$CC64 CFG_ARM64_core=y $OPTEE_EXTRA_ARGS \
      PLATFORM=$OPTEE_PLATFORM
  1. U-Boot:

  • 3.1 R5:

# inside u-boot source
make $UBOOT_CFG_CORTEXR
make CROSS_COMPILE=$CC32 BINMAN_INDIRS=$LNX_FW_PATH
  • 3.2 A72:

# inside u-boot source
make $UBOOT_CFG_CORTEXA
make CROSS_COMPILE=$CC64 BINMAN_INDIRS=$LNX_FW_PATH \
       BL31=$TFA_PATH/build/k3/$TFA_BOARD/release/bl31.bin \
       TEE=$OPTEE_PATH/out/arm-plat-k3/core/tee-raw.bin

Note

It is also possible to pick up a custom DM binary by adding TI_DM argument pointing to the file. If not provided, it defaults to picking up the DM binary from BINMAN_INDIRS. This is only applicable to devices that utilize split firmware.

Target Images

In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC variant (GP, HS-FS, HS-SE) requires a different source for these files.

  • GP

    • tiboot3-j721s2-gp-evm.bin from step 3.1

    • tispl.bin_unsigned, u-boot.img_unsigned from step 3.2

  • HS-FS

    • tiboot3-j721s2-hs-fs-evm.bin from step 3.1

    • tispl.bin, u-boot.img from step 3.2

  • HS-SE

Image formats:

  • tiboot3.bin

../../_images/multi_cert_tiboot3.bin.svg
  • tispl.bin

../../_images/dm_tispl.bin.svg

R5 Memory Map:

Region

Start Address

End Address

SPL

0x41c00000

0x41c40000

EMPTY

0x41c40000

0x41c61f20

STACK

0x41c65f20

0x41c61f20

Global data

0x41c65f20

0x41c66000

Heap

0x41c66000

0x41c76000

BSS

0x41c76000

0x41c80000

DM DATA

0x41c80000

0x41c84130

EMPTY

0x41c84130

0x41cff9fc

MCU Scratchpad

0x41cff9fc

0x41cffbfc

ROM DATA

0x41cffbfc

0x41cfffff

Switch Setting for Boot Mode

Boot Mode pins provide means to select the boot mode and options before the device is powered up. After every POR, they are the main source to populate the Boot Parameter Tables.

Boot Mode Pins for J721S2-EVM

The following table shows some common boot modes used on J721S2 platform. More details can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/spruj28 under the Boot Mode Pins section.

Boot Modes

Switch Label

SW9: 12345678

SW8: 12345678

SD

00000000

10000010

EMMC

01000000

10000000

OSPI

01000000

00000110

UART

01110000

00000000

USB DFU

00100000

10000000

For SW8 and SW9, the switch state in the “ON” position = 1.

Boot Mode Pins for SK-AM68

The following table shows some common boot modes used on AM68-SK platform. More details can be found in the User Guide for AM68-SK: https://www.ti.com/lit/pdf/spruj68 under the Bootmode Settings section.

Boot Modes

Switch Label

SW1: 1234

SD

0000

xSPI

0010

UART

1010

Ethernet

0100

For SW1, the switch state in the “ON” position = 1.

Debugging U-Boot

See Common Debugging environment - OpenOCD: for detailed setup information.

Warning

OpenOCD support since: v0.12.0

If the default package version of OpenOCD in your development environment’s distribution needs to be updated, it might be necessary to build OpenOCD from the source.

Debugging U-Boot on J721S2-EVM

Integrated JTAG adapter/dongle: The board has a micro-USB connector labelled XDS110 USB or JTAG. Connect a USB cable to the board to the mentioned port.

Note

There are multiple USB ports on a typical board, So, ensure you have read the user guide for the board and confirmed the silk screen label to ensure connecting to the correct port.

To start OpenOCD and connect to the board

openocd -f board/ti_j721s2evm.cfg

Debugging U-Boot on SK-AM68

cTI20 connector: The TI’s cTI20 connector is probably the most prevelant on TI platforms. Though many TI boards have an onboard XDS110, cTI20 connector is usually provided as an alternate scheme to connect alternatives such as Lauterbach or XDS560.

To debug on these boards, the following combinations is suggested:

Warning

XDS560 and Lauterbach are proprietary solutions and is not supported by OpenOCD. When purchasing an off the shelf adapter/dongle, you do want to be careful about the signalling though. Please read for additional info.

  • External JTAG adapter/interface: In other cases, where an adapter/dongle is used, a simple cfg file can be created to integrate the SoC and adapter information. See supported TI K3 SoCs to decide if the SoC is supported or not.

openocd -f openocd_connect.cfg

For SK-AM68, the openocd_connect.cfg is as follows:

# TUMPA example:
# http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual
source [find interface/ftdi/tumpa.cfg]

transport select jtag

# default JTAG configuration has only SRST and no TRST
reset_config srst_only srst_push_pull

# delay after SRST goes inactive
adapter srst delay 20

if { ![info exists SOC] } {
  # Set the SoC of interest
  set SOC j721s2
}

source [find target/ti_k3.cfg]

ftdi tdo_sample_edge falling

# Speeds for FT2232H are in multiples of 2, and 32MHz is tops
# max speed we seem to achieve is ~20MHz.. so we pick 16MHz
adapter speed 16000